1Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 Banks
MT41J128M8 – 16 Meg x 8 x 8 Banks
MT41J64M16 – 8 Meg x 16 x 8 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
VDD = VDDQ = +1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
TC of 0oC to 95oC
– 64ms, 8,192 cycle refresh at 0oC to 85oC
– 32ms at 85oC to 95oC
Clock frequency range of 300–800 MHz
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Table 1:
Marking
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) - x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev. F
– 78-ball FBGA (9mm x 11.5mm) Rev. D
– 86-ball FBGA (9mm x 15.5mm) Rev. B
• FBGA package (Pb-free) - x16
– 96-ball FBGA (9mm x 15.5mm) Rev. B
• Timing - cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.25ns @ CL = 10 (DDR3-1600)
– 1.25ns @ CL = 9 (DDR3-1600)
– 1.5ns @ CL = 10 (DDR3-1333)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.5ns @ CL = 8 (DDR3-1333)
– 1.87ns @ CL = 8 (DDR3-1066)
– 1.87ns @ CL = 7 (DDR3-1066)
– 2.5ns @ CL = 6 (DDR3-800)
– 2.5ns @ CL = 5 (DDR3-800)
• Revision
256M4
128M8
64M16
JP
HX
BY
LA
-125
-125E
-125F
-15
-15E
-15F
-187
-187E
-25
-25E
:B/:D/:F
Key Timing Parameters
Speed Grade
Data Rate (MT/s) Target tRCD-tRP-CL
tRCD
(ns)
13.75
tRP
(ns)
13.75
CL (ns)
-125
1600
11-11-11
13.75
-125E
1600
10-10-10
12.5
12.5
12.5
-125F
1600
9-9-9
11.25
11.25
11.25
-15
1333
10-10-10
15
15
15
-15E
1333
9-9-9
13.5
13.5
13.5
-15F
1333
8-8-8
12
12
12
-187
1066
8-8-8
15
15
15
-187E
1066
7-7-7
13.1
13.1
13.1
-25
800
6-6-6
15
15
15
-25E
800
5-5-5
12.5
12.5
12.5
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. F 11/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2:
Addressing
Parameter
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
32 Meg x 4 x 8 banks
16 Meg x 8 x 8 banks
8 Meg x 16 x 8 banks
Refresh count
8K
8K
8K
Row addressing
16K (A[13:0])
16K (A[13:0])
8K (A[12:0])
Bank addressing
8 (BA[2:0])
8 (BA[2:0])
8 (BA[2:0])
2K (A[11, 9:0])
1K (A[9:0])
1K (A[9:0])
Column addressing
Figure 1:
1Gb DDR3 Part Numbers
Example Part Number: M T 4 1 J 2 5 6 M 4 B Y- 1 5 : B
Package
Configuration
:
Speed
Revision
{
MT41J
:B/:D/:F
Revision
Temperature
Configuration
256 Meg x 4
256M4
Commercial
128 Meg x 8
128M8
Industrial temperature
64 Meg x 16
64M16
Package
Rev.
Mark
-125
Speed Grade
tCK = 1.25ns, CL = 11
78-ball 8mm x 11.5mm FBGA
F
JP
-125E
tCK = 1.25ns, CL = 10
78-ball 9mm x 11.5mm FBGA
D
HX
-125F
tCK = 1.25ns, CL = 9
86-ball 9mm x 15.5mm FBGA
B
BY
-15
tCK = 1.5ns, CL = 10
96-ball 9mm x 15.5mm FBGA
B
LA
-15E
tCK = 1.5ns, CL = 9
-15F
tCK = 1.5ns, CL = 8
-187
tCK = 1.87ns, CL = 8
-187E
tCK = 1.87ns, CL = 7
-25
tCK = 2.5ns, CL = 6
-25E
tCK = 2.5ns, CL = 5
None
IT
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA Part Marking Decoder on Micron’s Web site: www.micron.com.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. F 11/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Electrical Specifications – IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Electrical Characteristics – IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Slew Rate Definitions for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Slew Rate Definitions for Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
34Ω Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
34Ω Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Alternative 40Ω Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Output Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Reference Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Slew Rate Definitions for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Slew Rate Definitions for Differential Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Speed Bin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Command and Address Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Data Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
DESELECT (DES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Input Clock Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_TOC.fm - Rev. F 11/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Table of Contents
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Temperature Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nominal ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT Off During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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1Gb DDR3 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
256 Meg x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
128 Meg x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
64 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
78-Ball FBGA – x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
86-Ball FBGA – x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
96-Ball FBGA – x16 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
78-Ball FBGA – x4, x8; “JP” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
78-Ball FBGA – x4, x8; “HX” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
86-Ball FBGA – x4, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
96-Ball FBGA – x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Thermal Measurement Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IDD1 Example – DDR3-800, 5-5-5, x8 (-25E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IDD2N/IDD3N Example – DDR3-800, 5-5-5, x8 (-25E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
IDD4R Example – DDR3-800, 5-5-5, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Single-Ended Requirements for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Definition of Differential AC-Swing and tDVAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Nominal Slew Rate Definition for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . . . . . . . . . . .48
ODT Levels and I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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AON and tAOF Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
tAONPD and tAOFPD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
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ADC Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DQ Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Differential Output Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Reference Output Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Nominal Slew Rate Definition for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Nominal Differential Output Slew Rate Definition for DQS, DQS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . .80
Nominal Slew Rate for tIH (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Tangent Line for tIS (Command and Address – Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Tangent Line for tIH (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Nominal Slew Rate and tVAC for tDS (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Nominal Slew Rate for tDH (DQ – Strobe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Tangent Line for tDS (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Tangent Line for tDH (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
DLL Enable Mode to DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
DLL Disable Mode to DLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
DLL Disable tDQSCK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Change Frequency During Precharge Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Write Leveling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Exit Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
MRS-to-MRS Command Timing (tMRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MRS-to-nonMRS Command Timing (tMOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Mode Register 0 (MR0) Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Mode Register 1 (MR1) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
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READ Latency (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 2 (MR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register 3 (MR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multipurpose Register (MPR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPR System Read Calibration with BL8: Fixed Burst Order Single Readout. . . . . . . . . . . . . . . . . . .
MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout . . . . . . . . . . .
MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble. . . . . . . . . . . . . . . . . .
MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble. . . . . . . . . . . . . . . . . .
ZQ Calibration Timing (ZQCL and ZQCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example: tFAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive READ Bursts (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive READ Bursts (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ to PRECHARGE (BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ to PRECHARGE (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ to PRECHARGE (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ with Auto Precharge (AL = 4, CL = 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Timing – tDQSQ and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Strobe Timing – READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method for Calculating tLZ and tHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tRPRE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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WPRE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tWPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive WRITE (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE to READ (BC4 Mode Register Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE (BC4 OTF) to READ (BC4 OTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE (BL8) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE (BC4 Mode Register Setting) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE (BC4 OTF) to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Entry/Exit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Power-Down Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Power-Down (Fast-Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Power-Down (Slow-Exit Mode) Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Entry After READ or READ with Auto Precharge (RDAP) . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Entry After WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Entry After WRITE with Auto Precharge (WRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REFRESH to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVATE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRECHARGE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Exit to Refresh to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic ODT: Without WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
List of Figures
Figure 113:
Figure 114:
Figure 115:
Figure 116:
Figure 117:
Figure 118:
Figure 119:
Figure 120:
Figure 121:
Figure 122:
Figure 123:
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 . . . .
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4. . . . . . . . . . . . .
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4. . . . . . . . . . . . .
Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous ODT Timing with Fast ODT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry . . . .
Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit. . . . . .
Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping . . . . . . . . .
Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping. . . . . . . . .
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Table 33:
Table 34:
Table 35:
Table 36:
Table 37:
Table 38:
Table 39:
Table 40:
Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Table 49:
Table 50:
Table 51:
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
78-Ball FBGA – x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
86-Ball FBGA – x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
96-Ball FBGA – x16 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IDD Measurement Conditions Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Definition of Switching for Command and Address Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Definition of Switching for Data Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IDD Measurement Conditions for IDD0 and IDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
IDD Measurement Conditions for Power-Down Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
IDD Measurement Conditions for IDD4R, IDD4W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
IDD Measurement Conditions for IDD5B, IDD6, IDD6ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
IDD Measurement Conditions for IDD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
IDD7 Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
IDD Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Electrical Characteristics and Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Control and Address Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Differential Input Operating Conditions (CK, CK# and DQS, DQS#) . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS#. . . . . . . . . . . . . . . . . . . . . . . . .45
Single-Ended Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
On-Die Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
RTT Effective Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
ODT Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
ODT Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
34Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver Pull-Up and Pull-Down Impedance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
34Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
40Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Single-Ended Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Differential Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Single-Ended Output Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
DDR3-800 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
DDR3-1066 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
DDR3-1333 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
List of Tables
Table 52:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
Table 75:
Table 76:
Table 77:
Table 78:
Table 79:
Table 80:
Table 81:
Table 83:
DDR3-1600 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based . . . . . . . . . . .77
DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tIS/tIH – AC/DC-Based78
DDR3-1333 and DDR3-1600 Derating Values for tIS/tIH – AC/DC-Based . . . . . . . . . . . . . . . . . . . . . . .78
Minimum Required Time tVAC Above VIH(AC) for Valid Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based . . . . . . . . . . . . . . . . . .84
DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 Derating Values for tDS/tDH – AC/DC-Based85
DDR3-1333and DDR3-1600 Derating Values for tDS/tDH – AC/DC-Based . . . . . . . . . . . . . . . . . . . . .85
Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid Transition. . . . . . . . . . . . . . . . . . . . . . . .86
Truth Table – Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
READ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
WRITE Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
READ Electrical Characteristics, DLL Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Write Leveling Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MPR Functional Description of MR3 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MPR Readouts and Burst Order Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Self Refresh Temperature and Auto Self Refresh Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Self Refresh Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Command to Power-Down Entry Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Truth Table – ODT (Nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
ODT Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Dynamic ODT Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Mode Registers for Rtt_nom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Mode Registers for Rtt_wr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Timing Diagrams for Dynamic ODT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Synchronous ODT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period . . . . . . . . . . . . . . . . 175
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_LOT.fm - Rev. F 11/08 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
CKE L
Power
applied
Power
on
Reset
procedure
MRS, MPR,
write
leveling
Initialization
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Idle
Refreshing
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
READ AP
READ
Writing
READ
WRITE
Reading
READ AP
WRITE AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Precharging
Reading
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
10
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Functional Description
Functional Description
The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or write
access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control,
command, and address signals are registered at every positive edge of CK. Input data is
registered on the first rising edge of DQS after the WRITE preamble, and output data is
referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE commands are used to select the
bank and the starting column location for the burst access.
DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row
precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise.
• The terms “DQS” and “CK” found throughout the data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document, and any
page or diagram may have been simplified to convey a topic and may not be inclusive
of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal,
and not supported and can result in unknown operation.
• Row addressing is denoted as A[n:0](1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3:
256 Meg x 4 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQCL, ZQCS
CKE
VSSQ
To pull-up/pull-down
networks
ZQ CAL
RESET#
Control
logic
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
Rowaddress
MUX
16
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
14
14
16,384
RTT_WR
CK, CK#
sw2
sw1
DLL
(1 . . . 4)
14
Bank 0
rowaddress
latch
and
decoder
RTT_NOM
Columns 0, 1, and 2
Bank 0
memory
array
(16,384 x 256 x 32)
32
READ
FIFO
and
data
MUX
4
DQ[3:0]
READ
drivers
DQ[3:0]
DQS, DQS#
VDDQ/2
Sense amplifiers
32
BC4
RTT_NOM
8,192
BC4
OTF
I/O gating
DM mask logic
3
A[13:0]
BA[2:0]
17
Address
register
3
sw1
(1, 2)
Columnaddress
counter/
latch
DQS, DQS#
VDDQ/2
32
Data
interface
Column
decoder
4
Data
WRITE
drivers
and
input
logic
8
RTT_NOM
sw1
RTT_WR
sw2
DM
3
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
sw2
DM
Bank
control
logic
256
(x32)
11
RTT_WR
12
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Figure 4:
128 Meg x 8 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQ CAL
ZQCL, ZQCS
A12
CK, CK#
VDDQ/2
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
16
14
sw2
sw1
DLL
(1 . . . 8)
Bank 0
memory
array
(16,384 x 128 x 64)
Bank 0
rowaddress
16,384
latch
and
decoder
14
RTT_WR
CK, CK#
14
Rowaddress
MUX
RTT_NOM
64
DQ8
READ
FIFO
and
data
MUX
8
TDQS#
DQ[7:0]
READ
drivers
DQ[7:0]
DQS, DQS#
VDDQ/2
Sense amplifiers
64
BC4
8,192
17
Address
register
(1, 2)
Bank
control
logic
3
64
8
Data
interface
Data
Column
decoder
Columnaddress
counter/
latch
10
RTT_NOM
RTT_WR
sw2
sw1
DM/TDQS
(shared pin)
3
Columns 0, 1, and 2
Column 2
(select upper or
lower nibble for BC4)
64 Meg x 16 Functional Block Diagram
ODT
control
ODT
ZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
WRITE
drivers
and
input
logic
7
CK, CK#
RZQ
DQS, DQS#
VDDQ/2
(128
x64)
Figure 5:
RTT_WR
sw2
sw1
I/O gating
DM mask logic
3
A[13:0]
BA[2:0]
BC4
OTF
RTT_NOM
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
16
13
13
Bank 0
rowaddress
latch
and
decoder
8,192
RTT_WR
CK, CK#
sw2
sw1
DLL
(1 . . . 16)
13
Rowaddress
MUX
RTT_NOM
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
memory
array
(8192 x 128 x 128)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
LDQS, LDQS#, UDQS, UDQS#
DQ[15:0]
VDDQ/2
Sense amplifiers
BC4
128
16,384
Address
register
3
LDQS, LDQS#
I/O gating
DM mask logic
3
16
Bank
control
logic
(1 . . . 4)
128
Data
interface
Column
decoder
Columnaddress
counter/
latch
16
Data
WRITE
drivers
and
input
logic
RTT_NOM
sw1
RTT_WR
sw2
7
(1, 2)
LDM/UDM
3
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
UDQS, UDQS#
VDDQ/2
(128
x128)
10
RTT_WR
sw2
sw1
BC4
OTF
A[12:0]
BA[2:0]
RTT_NOM
13
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 6:
78-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5 VDDQ
VDDQ NF, DQ4
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
G
H
J
K
L
M
N
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. Ball descriptions listed in Table 3 on page 17 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 3 on page 17).
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Figure 7:
86-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
2
3
4
5
6
7
8
9
A
NC
NC
NC
NC
B
C
D
VSS
VDD
NC
NF, NF/TDQS#
VSS
VDD
VSS
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
E
F
G
VSSQ
H
VREFDQ
NF, DQ7 NF, DQ5
VDDQ NF, DQ4
VDDQ
J
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
NC
NC
K
L
M
N
P
R
T
U
V
W
NC
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
NC
1. Ball descriptions listed in Table 4 on page 19 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 4 on page 19).
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Figure 8:
96-Ball FBGA – x16 Ball Assignments (Top View)
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
NC
NC
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. Ball descriptions listed in Table 5 on page 21 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 5 on page 21).
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3:
78-Ball FBGA – x4, x8 Ball Descriptions
Ball Assignments
Symbol
Type
Description
K3, L7, L3, K2,
L8, L2, M8, M2,
N8, M3, H7, M7,
K7, N3
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9, A10/AP,
A11, A12/BC#,
A13
Input
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
See Table 62 on page 91.
J2, K8, J3
BA0, BA1, BA2
Input
Bank address inputs: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
F7, G7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
G9
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
H2
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
B7
DM
Input
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with the input data
during a write access. Although the DM ball is input-only, the DM
loading is designed to match that of the DQ and DQS balls. DM is
referenced to VREFDQ. DM has an optional use as TDQS on the x8.
G1
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to
VREFCA.
F3, G3, H3
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3:
78-Ball FBGA – x4, x8 Ball Descriptions (continued)
Ball Assignments
Symbol
Type
Description
N2
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
B3, C7,
C2, C8
DQ0, DQ1,
DQ2, DQ3
I/O
Data input/output: Bidirectional data bus for the x4 configuration.
DQ[3:0] are referenced to VREFDQ.
B3, C7, C2,
C8, E3, E8,
D2, E7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
I/O
Data input/output: Bidirectional data bus for the x8 configuration.
DQ[7:0] are referenced to VREFDQ.
C3, D3
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
B7, A7
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only.
When TDQS is enabled, DM is disabled, and the TDQS and TDQS#
balls provide termination resistance.
A2, A9, D7, G2, G8,
K1, K9, M1, M9
VDD
Supply
Power supply: 1.5V ±0.075V.
B9, C1, E2, E9
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
J8
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
E1
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
A1, A8, B1, D8, F2,
F8, J1, J9, L1, L9, N1,
N9
VSS
Supply
Ground.
B2, B8, C9, D1, D9
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
H8
ZQ
A3, J7, N7, F9, H1, F1,
H9
NC
–
No connect: These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
A7, D2, E3, E7, E8
NF
–
No function: When configured as a x4 device, these balls are NF.
When configured as a x8 device, these balls are defined as TDQS#,
DQ[7:4].
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Reference External reference ball for output drive calibration: This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 4:
86-Ball FBGA – x4, x8 Ball Descriptions
Ball Assignments
Symbol
Type
Description
N3, P7, P3, N2,
P8, P2, R8, R2,
T8, R3,
L7,
R7, N7,
T3
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9
A10/AP,
A11, A12/BC#,
A13
Input
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
See Table 62 on page 91.
M2, N8, M3
BA0, BA1, BA2
Input
Bank address inputs: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
J7, K7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
K9
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
L2
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
E7
DM
Input
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with the input data
during a write access. Although the DM ball is input-only, the DM
loading is designed to match that of the DQ and DQS balls. DM is
referenced to VREFDQ. DM has an optional use as TDQS on the x8.
K1
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to
VREFCA.
J3, K3, L3
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 4:
86-Ball FBGA – x4, x8 Ball Descriptions (continued)
Ball Assignments
Symbol
Type
Description
T2
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
E3, F7,
F2, F8
DQ0, DQ1,
DQ2, DQ3
I/O
Data input/output: Bidirectional data bus for the x4 configuration.
DQ[3:0] are referenced to VREFDQ.
E3, F7, F2,
F8, H3, H8,
G2, H7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
I/O
Data input/output: Bidirectional data bus for the x8 configuration.
DQ[7:0] are referenced to VREFDQ.
F3, G3
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
E7, D7
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only.
When TDQS is enabled, DM is disabled, and the TDQS and TDQS#
balls provide termination resistance.
D2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power supply: 1.5V ±0.075V.
E9, F1, H2, H9
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
M8
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
H1
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
D1, D8, E1, G8, J2, J8,
M1, M9, P1, P9, T1,
T9
VSS
Supply
Ground.
E2, E8, F9, G1, G9
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
L8
ZQ
A1, A3, A7, A9, D3,
J1, J9, L1, L9, M7, T7,
W1, W3, W7, W9
NC
–
No connect: These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
D7, G2, H3, H7, H8
NF
–
No function: When configured as a x4 device, these balls are NF.
When configured as a x8 device, these balls are defined as TDQS#,
DQ[7:4].
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Reference External reference ball for output drive calibration: This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 5:
96-Ball FBGA – x16 Ball Descriptions
Ball Assignments
Symbol
Type
Description
N3, P7, P3, N2,
P8, P2, R8, R2,
T8, R3,
L7,
R7, N7
A0, A1, A2, A3,
A4, A5, A6, A7,
A8, A9
A10/AP,
A11, A12/BC#
Input
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See
Table 62 on page 91.
M2, N8, M3
BA0, BA1, BA2
Input
Bank address inputs: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
J7, K7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
K9
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle),or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
L2
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to VREFCA.
E7
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write
data. Lower-byte input data is masked when LDM is sampled HIGH
along with the input data during a write access. Although the LDM
ball is input-only, the LDM loading is designed to match that of the
DQ and DQS balls. LDM is referenced to VREFDQ.
K1
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#,
LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/
TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and
DM for the x4. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to VREFCA.
J3, K3, L3
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to VREFCA.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 5:
96-Ball FBGA – x16 Ball Descriptions (continued)
Ball Assignments
Symbol
Type
Description
T2
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET#
assertion and desertion are asynchronous.
D3
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for
write data. Upper-byte input data is masked when UDM is sampled
HIGH along with that input data during a WRITE access. Although
the UDM ball is input-only, the UDM loading is designed to match
that of the DQ and DQS balls. UDM is referenced to VREFDQ.
E3, F7, F2,
F8, H3, H8,
G2, H7
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
I/O
Data input/output: Lower byte of bidirectional data bus for the x16
configuration. DQ[7:0] are referenced to VREFDQ.
D7, C3,
C8, C2,
A7, A2,
B8, A3
DQ8, DQ9,
DQ10, DQ11,
DQ12, DQ13,
DQ14, DQ15
I/O
Data input/output: Upper byte of bidirectional data bus for the x16
configuration. DQ[15:8] are referenced to VREFDQ.
F3, G3
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned
with read data. Input with write data. Center-aligned to write data.
C7, B7
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with
read data. Input with write data. DQS is center-aligned to write data.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power supply: 1.5V ±0.075V.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
M8
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA
must be maintained at all times (including self refresh) for proper
device operation.
H1
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all
times (including self refresh) for proper device operation.
A9, B3, E1, G8, J2, J8,
M1, M9, P1, P9, T1,
T9
VSS
Supply
Ground.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
L8
ZQ
J1, J9, L1, L9, M7, T3,
T7
NC
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Reference External reference ball for output drive calibration: This ball is
tied to an external 240Ω resistor (RZQ), which is tied to VSSQ.
–
No connect: These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Package Dimensions
Figure 9:
78-Ball FBGA – x4, x8; “JP”
0.8 ±0.1
Seating
plane
0.12 A
A
78X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.33
NSMD ball pads.
8 ±0.15
9
8
7
3
2
Ball A1 ID
1
Ball A1 ID
A
B
C
D
0.8 TYP
E
F
9.6
CTR
G
11.5 ±0.15
H
J
K
L
M
N
0.8
TYP
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1.2 MAX
6.4 CTR
0.25 MIN
1. All dimensions are in millimeters.
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 10: 78-Ball FBGA – x4, x8; “HX”
0.8 ±0.1
Seating
plane
0.12 A
A
78X Ø0.45
Solder ball
material: SAC305.
Dimensions apply to
solder balls postreflow on Ø0.33
NSMD ball pads.
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
9.6
CTR
G
11.5 ±0.15
H
J
K
L
M
0.8 TYP
N
0.8 TYP
1.2 MAX
0.25 MIN
6.4 CTR
9 ±0.15
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. All dimensions are in millimeters.
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 11: 86-Ball FBGA – x4, x8
0.8 ±0.1
Seating
plane
0.12 A
A
86X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.33 NSMD
ball pads.
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
D
0.8 TYP
E
F
G
H
J
14.4 CTR
K
15.5 ±0.15
L
M
N
P
R
T
2.4 TYP
W
0.8 TYP
1.2 MAX
0.25 MIN
6.4 CTR
9 ±0.15
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. All dimensions are in millimeters.
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 12: 96-Ball FBGA – x16
0.8 ±0.1
Seating
plane
0.12 A
A
96X Ø0.45
Solder ball
material: SAC305.
Dimensions
apply to solder
balls post-reflow
on Ø0.33 NSMD
ball pads.
Ball A1 ID
Ball A1 ID
9
8
7
3
2
1
A
B
C
D
E
F
G
H
12 CTR
15.5 ±0.15
J
K
L
M
N
P
R
0.8 TYP
S
0.8 TYP
1.2 MAX
0.25 MIN
6.4 CTR
9 ±0.15
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. All dimensions are in millimeters.
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
adversely affect reliability.
Table 6:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
TC
Operating case temperature
0
95
°C
TSTG
Storage temperature
–55
150
°C
Notes:
2, 3
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV.
2. MAX operating case temperature. TC is measured in the center of the package (see
Figure 13 on page 28).
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during
operation.
Input/Output Capacitance
Table 7:
Input/Output Capacitance
Note 1 applies to the entire table
Capacitance Parameters
DDR3-800
DDR3-1066 DDR3-1333 DDR3-1600
Symbol
Min
Max
Min
Max
Min
Max
Min
CK and CK#
CCK
0.8
1.6
0.8
1.6
0.8
1.4
0.8
Max Units Notes
1.4
ΔC: CK to CK#
pF
CDCK
0
0.15
0
0.15
0
0.15
0
0.15
pF
Single-end I/O: DQ, DM
CIO
1.5
3.0
1.5
3.0
1.5
2.5
1.5
2.3
pF
2
Differential I/O:
DQS, DQS#, TDQS, TDQS#
CIO
1.5
3.0
1.5
3.0
1.5
2.5
1.5
2.3
pF
3
CDDQS
0
0.2
0
0.2
0
0.15
0
0.15
pF
3
ΔC: DQS to DQS#, TDQS, TDQS#
ΔC: DQ to DQS
Inputs (CTRL, CMD, ADDR)
ΔC: CTRL to CK
ΔC: CMD_ADDR to CK
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
CDIO
–0.5
0.3
–0.5
0.3
–0.5
0.3
–0.5
0.3
pF
4
CI
0.75
1.5
0.75
1.5
0.75
1.3
0.75
1.3
pF
5
CDI_CTRL
–0.5
0.3
–0.5
0.3
–0.4
0.2
–0.4
0.2
pF
6
CDI_CMD_ADDR
–0.5
0.5
–0.5
0.5
–0.4
0.4
–0.4
0.4
pF
7
1. VDD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C.
VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V.
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO (DQ) - 0.5 × (CIO [DQS] + CIO [DQS#]).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0],
BA[2:0].
6. CDI_CTRL = CI (CTRL) - 0.5 × (CCK [CK] + CCK [CK#]).
7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Thermal Characteristics
Thermal Characteristics
Table 8:
Thermal Characteristics
Parameter/Condition
Operating case temperature
Junction-to-case (TOP)
Notes:
78-ball
Symbol
Value
Units
Notes
TC
0 to 85
°C
1, 2, 3
TC
0 to 95
°C
1, 2, 3, 4
ΘJC
3.2
°C/W
5
86-ball
2.8
96-ball
2.8
1. MAX operating case temperature. TC is measured in the center of the package (see
Figure 13).
2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate. The use of SRT or ASR (if available) must be enabled.
5. The thermal resistance data is based off of a number of samples from multiple lots and
should be viewed as a typical number.
Figure 13: Thermal Measurement Point
(L/2)
Tc test point
L
(W/2)
W
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1Gb_DDR3_D2.fm - Rev. F 11/08 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Electrical Specifications – IDD Specifications and Conditions
The following definitions are used within the IDD measurement tables:
• LOW: VIN ≤ VIL(AC) MAX; HIGH: VIN ≥ VIH(AC) MIN
• Stable: Inputs are stable at a HIGH or LOW level
• Floating: Inputs are VREF = VDDQ/2
• Switching: See Tables 10 and 11
Table 9:
Table 10:
IDD Measurement Conditions Reference
Table Number
Measurement Conditions
Table 13 on page 31
IDD0 and IDD1
Table 14 on page 33
IDD2Ps, IDD2Pf, IDD2Q, IDD2N, IDD3P, and IDD3N
Table 15 on page 35
IDD4R, IDD4W
Table 16 on page 37
IDD5B, IDD6, IDD6ET
Table 17 on page 38
IDD7 (see Table 18 on page 38)
Definition of Switching for Command and Address Input Signals
Switching for Address (Row/Column) and Command Signals (CS#, RAS#, CAS#, and/or WE#)
Address (row/column)
If not otherwise stated, inputs are stable at HIGH or LOW during 4 clocks and then change to
the opposite value (Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax . . . )
Bank address
If not otherwise stated, the bank addresses should be switched in a similar fashion as the
row/column addresses
Command
(CS#, RAS#, CAS#, WE#)
Define command background pattern = D D D D D D D D D D D D . . . where:
D = (CS#, RAS#, CAS#, WE#) = (HIGH, LOW, LOW, LOW)
D = (CS#, RAS#, CAS#, WE#) = (HIGH, HIGH, HIGH, HIGH)
If other commands are necessary (ACTIVATE for IDD0 or READ for IDD4R), the background
pattern command is substituted by the respective CS#, RAS#, CAS#, and WE# levels of the
necessary command
Table 11:
Definition of Switching for Data Pins
Switching for Data Pins (DQ, DQS, DM)
Data strobe (DQS)
Data strobe is changing between HIGH and LOW after every clock cycle
Data (DQ)
Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for
DQ signals, which means that data DQ is stable during one clock
Data masking (DM)
No switching; DM must always be driven LOW
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1Gb_DDR3_D2.fm - Rev. F 11/08 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 12:
Timing Parameters
DDR3-800
-25E
IDD Parameter
t
5-5-5
CK (MIN) IDD
CL IDD
DDR3-1066
DDR3-1600
-25
-187E
-187
-15F
-15E
-15
-125F
6-6-6
7-7-7
8-8-8
8-8-8
9-9-9
10-10-10
9-9-9
2.5
5
DDR3-1333
1.875
1.5
1.25
15
13.13
15
12
13.5
15
11.25
12.5
13.75
ns
50
52.5
50.63
52.50
48
49.5
51
46.25
47.5
48.75
ns
RAS (MIN) IDD
37.5
37.5
37.5
37.5
36
36
36
35
35
35
ns
RP (MIN)
12.5
15
13.13
15
12
13.5
15
11.25
12.5
13.75
ns
x4, x8
40
40
37.5
37.5
30
30
30
30
30
30
ns
x16
50
50
50
50
45
45
45
40
40
40
ns
x4, x8
10
10
7.5
7.5
6
6
6
6
6
6
ns
x16
10
10
10
10
7.5
7.5
7.5
7.5
7.5
7.5
ns
110
110
110
110
110
110
110
110
110
110
ns
RC (MIN) IDD
t
t
t
FAW
tRRD IDD
tRFC
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1.
2.
3.
4.
10
9
10
ns
12.5
RCD (MIN) IDD
9
10-10-10 11-11-11 Units
7
t
8
-125
6
t
8
-125E
11
CK
IDD specifications are tested after the device is properly initialized.
Input slew rate is specified by AC parametric test conditions.
IDD parameters are specified with ODT and the output buffer is disabled (MR1[12]).
Optional ASR is disabled unless stated otherwise.
30
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 13:
IDD Measurement Conditions for IDD0 and IDD1
IDD Test
IDD0: Operating Current 0
One Bank ACTIVATE to PRECHARGE
IDD1: Operating Current 1
One Bank ACTIVATE to READ
to PRECHARGE
–
Figure 14 on page 32
HIGH
HIGH
Timing example
CKE
External clock
t
On
CK
t
tRC
t
On
t
CK (MIN) IDD
CK (MIN) IDD
t
RC (MIN) IDD
RC (MIN) IDD
t
RAS (MIN) IDD
t
tRCD
n/a
t
tRAS
RAS (MIN) IDD
RCD (MIN) IDD
tRRD
n/a
tRC
n/a
n/a
CL
n/a
CL IDD
n/a
AL
n/a
0
CS#
HIGH between ACTIVATE and PRECHARGE
HIGH between ACTIVATE, READ, and
PRECHARGE
Switching—the only exceptions are
ACTIVATE and PRECHARGE commands;
Example of -25E IDD0 pattern:
A0DDDDDDDDDDDDDDP0
Switching—the only exceptions are
ACTIVATE and PRECHARGE commands;
Example of -25E IDD1 pattern:
A0DDDDR0DDDDDDDDDP0
Command inputs
Row/column addresses
Row addresses switching;
Row addresses switching;
Address input A10 must be LOW at all times Address input A10 must be LOW at all times
Bank addresses
Data I/O
Output buffer DQ, DQS
ODT
Bank address is fixed (bank 0)
Bank address is fixed (bank 0)
Switching
Read data: Output data switches after
every clock cycle, which means that read
data is stable during falling DQS; I/O should
be floating when no read data
Off
Off
Disabled
Disabled
Burst length
n/a
8 fixed (via MR0)
Active banks
Bank 0; ACTIVATE-to-PRECHARGE loop
Bank 0; ACTIVATE-to-READ-to-PRECHARGE
loop
All other
All other
n/a
n/a
Idle banks
Special notes
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Notes
1
1
2
1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
31
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Figure 14: IDD1 Example – DDR3-800, 5-5-5, x8 (-25E)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T12
T11
T13
T14
T15
T16
T17
T18
CK
BA[2:0]
A[9:0]
0
000
3FF
000
3FF
000
0
3
0
3
0
3FF
A10
A[12:11]
CS#
RAS#
CAS#
WE#
Command
ACT
D
D#
D#
D
RD
D#
D#
D
D
D#
0
DQ
D#
D
D
0 1 1 0 0 1
D#
PRE
D
D
D# D#
1
DM
IDD1 measurement loop
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to
achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are
MR1[12] = 1). Address inputs are split into three parts.
32
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©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 14:
IDD Measurement Conditions for Power-Down Currents
Name
IDD2Ps
IDD2Pf
Precharge
Precharge
Power-Down Power-Down
Current
Current
(Slow Exit)1
(Fast Exit)1
Timing example
CKE
External clock
t
CK
tRC
t
t
IDD2Q
Precharge
Quiet
Standby
Current
IDD2N
Precharge
Standby
Current
IDD3P
Active
Power-Down
Current
IDD3N
Active
Standby
Current
n/a
n/a
n/a
Figure 15 on
page 34
n/a
Figure 15 on
page 34
LOW
LOW
HIGH
HIGH
LOW
HIGH
On
On
On
On
On
CK (MIN) IDD
n/a
t
CK(MIN) IDD
n/a
t
CK(MIN) IDD
n/a
t
CK (MIN) IDD
n/a
t
CK (MIN) IDD
n/a
Notes
On
t
CK (MIN) IDD
n/a
RAS
n/a
n/a
n/a
n/a
n/a
n/a
tRCD
n/a
n/a
n/a
n/a
n/a
n/a
tRRD
n/a
n/a
n/a
n/a
n/a
n/a
tRC
n/a
n/a
n/a
n/a
n/a
n/a
CL
n/a
n/a
n/a
n/a
n/a
n/a
AL
n/a
n/a
n/a
n/a
n/a
n/a
CS#
Stable
Stable
HIGH
HIGH
Stable
HIGH
Command inputs
Stable
Stable
Stable
Switching
Stable
Switching
2
Row/column
addresses
Stable
Stable
Stable
Switching
Stable
Switching
2
Bank addresses
Data I/O
Output buffer
DQ, DQS
ODT
Stable
Stable
Stable
Switching
Stable
Switching
2
Floating
Floating
Floating
Switching
Floating
Switching
3
Off
Off
Off
Off
Off
Off
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Burst length
n/a
n/a
n/a
n/a
n/a
n/a
Active banks
None
None
None
None
All
All
Idle banks
All
All
All
All
None
None
Special notes
n/a
n/a
n/a
n/a
n/a
n/a
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit,
MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2. For further definition of input switching, see Table 10 on page 29.
3. For further definition of data switching, see Table 11 on page 29.
33
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Figure 15: IDD2N/IDD3N Example – DDR3-800, 5-5-5, x8 (-25E)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
D#
D#
T10
CK
BA[2:0]
0
7
0
A[12:0]
0000
1FFF
0000
CS#
RAS#
CAS#
WE#
Command
DQ[7:0]
D#
FF
00
D#
00
FF
D
FF
00
D
00
FF
D#
FF
D#
00
00
FF
D
FF
00
D
00
FF
FF
00
00
FF
D
FF
00
DM
IDD2N/IDD3N measurement loop
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
34
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©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 15:
IDD Measurement Conditions for IDD4R, IDD4W
IDD Test
IDD4R: Burst Read Operating Current
Timing diagram example
Figure 16 on page 36
–
HIGH
HIGH
CKE
External clock
t
IDD4W: Burst Write Operating Current Notes
On
t
CK
On
t
CK (MIN) IDD
CK (MIN) IDD
tRC
n/a
n/a
t
RAS
n/a
n/a
t
RCD
n/a
n/a
t
RRD
n/a
n/a
t
RC
CL
n/a
n/a
CL IDD
CL IDD
AL
0
0
CS#
HIGH between valid commands
HIGH between valid commands
Switching;
READ command/pattern:
R0DDDR1DDDR2DDDR3DDDR4 . . .
Rx = READ from bank x
Switching;
WRITE command/pattern:
W0DDDW1DDDW2DDDW3DDDW4 . . .
Wx = WRITE to bank x
1
Column addresses switching;
Address input A10 must always be LOW
Column addresses switching;
Address input A10 must always be LOW
1
Command inputs
Row/column addresses
Bank addresses
Bank address looping (0-to-1-to-2-to-3 . . . ) Bank address looping (0-to-1-to-2-to-3 . . . )
Data I/O
Seamless read data burst (BL8): Output
Seamless write data burst (BL8): Input data
data switches after every clock cycle, which
switches after every clock cycle, which
means that read data is stable during
means that write data is stable during
falling DQS
falling DQS
Output buffer DQ, DQS
Off
Off
Disabled
Disabled
Burst length
8 fixed (via MR0)
8 fixed (via MR0)
Active banks
All
All
ODT
Idle banks
Special notes
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
None
None
n/a
DM always LOW
2
1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
35
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Figure 16:
IDD4R Example – DDR3-800, 5-5-5, x8
T0
T1
T2
T4
T3
T5
T6
T8
T7
T9
T10
T12
T11
CK
BA[2:0]
0
1
2
3
A[9:0]
000
3FF
000
3FF
0
3
0
3
A10
A[12:11]
CS#
RAS#
CAS#
WE#
CMD[2:0]
RD
D
D#
D#
RD
D
DQ[7:0]
D#
D#
RD
D
D#
D#
RD
D
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
DM
Start measurement loop
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to
achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are
MR1[12] = 1). Address inputs are split into three parts.
36
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©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 16:
IDD Measurement Conditions for IDD5B, IDD6, IDD6ET
IDD5B: Refresh
Current
IDD Test
CKE
External clock
IDD6: Self Refresh Current
IDD6ET: Self Refresh Current
Normal Temperature Range Extended Temperature Range
TC = 0°C to 85°C
TC = 0°C to 95°C
Notes
HIGH
LOW
LOW
On
Off, CK and CK# = LOW
Off, CK and CK# = LOW
CK (MIN) IDD
n/a
n/a
RC
n/a
n/a
n/a
t
RAS
n/a
n/a
n/a
t
RCD
n/a
n/a
n/a
t
RRD
n/a
n/a
n/a
t
CK
t
t
tRC
tRFC
(MIN) IDD
n/a
n/a
CL
n/a
n/a
n/a
AL
n/a
n/a
n/a
CS#
HIGH between valid
commands
Floating
Floating
Switching
Floating
Floating
Command inputs
1
Row/column addresses
Switching
Floating
Floating
1
Bank addresses
Switching
Floating
Floating
1
Data I/O
Switching
Floating
Floating
2
Output buffer DQ, DQS
Disabled
Disabled
Disabled
ODT
Disabled
Disabled
Disabled
Burst length
n/a
n/a
n/a
Active banks
REFRESH command
every tRFC (MIN)
n/a
n/a
None
n/a
n/a
n/a
SRT disabled
SRT enabled
Idle banks
Special notes
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
37
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©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 17:
IDD Measurement Conditions for IDD7
IDD Test
IDD7: All Banks Interleaved Read Current
CKE
HIGH
External clock
On
t
CK
t
CK (MIN) IDD
tRC
t
RC (MIN) IDD
tRAS
t
RAS (MIN) IDD
tRCD
t
RCD (MIN) IDD
tRRD
t
RRD (MIN) IDD
tRC
n/a
CL
CL IDD
AL
CL - 1
CS#
HIGH between valid commands
Command inputs
See Table 10 on page 29 for patterns
Row/column addresses
Stable during DESELECTs (DES)
Bank addresses
Looping (see Table 10 on page 29 for patterns)
Data I/O
Read data (BL8): output data switches after every clock cycle, which means that read data is
stable during falling DQS; I/O should be floating when no read data is being driven
Output buffer DQ, DQS
Off
ODT
Disabled
Burst length
8 fixed (via MR0)
Active banks
All, rotational
Idle banks
n/a
Table 18:
IDD7 Patterns
Speed Bin
Width IDD7 Pattern
DDR3-800
(-25, -25E)
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7
D D A0 . . .
x16
DDR3-1066
(-187, -187E)
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
x16
DDR3-1333
(-15, -15E, -15F)
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5
RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 . . .
x4, x8 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
x16
DDR3-1600
(-125E, -125F, -125)
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D
A7 RA7 D D D D D D A0 . . .
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D
A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 . . .
x4, x8 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D
D A6 RA6 D D D A7 RA7 D D D D D D D A0 . . .
x16
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D
D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D D D D A0 . . .
1. A0 = ACTIVATE bank 0; RA0 = READ with auto precharge bank 0; D = DESELECT.
38
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Characteristics – IDD Specifications
Electrical Characteristics – IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise
noted.
Table 19:
IDD Maximum Limits
Speed Bin
IDD
Width
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Notes
IDD0
x4
65
75
85
95
mA
1, 2
IDD1
x8
90
100
110
120
mA
1, 2
x16
90
100
110
120
mA
1, 2
x4
85
95
105
115
mA
1, 2
x8
110
120
130
140
mA
1, 2
x16
110
130
150
170
mA
1, 2
IDD2P0
Slow
10
10
10
10
mA
1, 2
IDD2P1
Fast
25
25
30
35
mA
1, 2
IDD2Q
All
45
50
55
60
mA
1, 2
IDD2N
All
50
55
60
65
mA
1, 2
1, 2
IDD3P
All
25
30
35
40
mA
IDD3N
x4, x8
50
55
60
65
mA
1, 2
x16
50
55
60
65
mA
1, 2
x4
130
160
200
250
mA
1, 2
x8
130
160
200
250
mA
1, 2
x16
190
230
270
315
mA
1, 2
1, 2
IDD4R
IDD4W
x4
130
160
190
225
mA
x8
130
160
190
225
mA
1, 2
x16
210
265
325
400
mA
1, 2
IDD5B
All
200
220
240
260
mA
1, 2
IDD6
All
7
7
7
7
mA
1, 2, 3
IDD6ET
All
9
9
9
9
mA
2, 4
IDD7
x4
230
250
315
400
mA
1, 2
x8
350
390
490
600
mA
1, 2
x16
350
380
420
460
mA
1, 2
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
1.
2.
3.
4.
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC (MAX) = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
39
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
DC Operating Conditions
Table 20:
DC Electrical Characteristics and Operating Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Supply voltage
I/O supply voltage
Input leakage current
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes:
Min
Nom
Max
Units
Notes
VDD
1.425
1.5
1.575
V
1, 2
VDDQ
1.425
1.5
1.575
V
1, 2
II
–2
–
2
µA
IVREF
–1
–
1
µA
3, 4
1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC
(0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing
parameters.
3. VREF (see Table 21).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin
should be minimal.
Input Operating Conditions
Table 21:
DC Electrical Characteristics and Input Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Units
Notes
Input reference voltage command/address bus
VREFCA(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
1, 2
I/O reference voltage DQ bus
VREFDQ(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
2, 3
VTT
–
0.5 × VDDQ
–
V
4
Command/address termination voltage
(system level, not direct DRAM input)
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level.
Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1 percent
× VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2
percent of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1
percent × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not
exceed ±2 percent of VREFDQ(DC).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent.
40
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1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Table 22:
AC Input Operating Conditions
Parameter/Condition
DDR3-800
DDR3-1066
Symbol
DDR3-1333
DDR3-1600
Units
Command and Address
Input high AC voltage: Logic 1
VIH(AC) MIN
+175
+150 or +175
mV
Input high DC voltage: Logic 1
VIH(DC) MIN
+100
+100
mV
Input low DC voltage: Logic 0
VIL(DC) MAX
–100
–100
mV
Input low AC voltage: Logic 0
VIL(AC) MAX
–175
–150 or –175
mV
DQ and DM
Input high AC voltage: Logic 1
VIH(AC) MIN
+175
+150
mV
Input high DC voltage: Logic 1
VIH(DC) MIN
+100
+100
mV
Input low DC voltage: Logic 0
VIL(DC) MAX
–100
–100
mV
Input low AC voltage: Logic 0
VIL(AC) MAX
–175
–150
mV
Notes:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and
DM inputs.
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV
(peak-to-peak).
5. For VIH(AC) and VIL(AC) levels of 150mV, special setup and hold derating and different tVAC
numbers apply.
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Figure 17: Input Signal
VIL and VIH levels with ringback
1.90V
VDDQ + 0.4V narrow
pulse width
1.50V
VDDQ
0.925V
VIH(AC)
0.850V
VIH(DC)
Minimum VIL and VIH levels
0.925V
0.850V
VIH(AC)
VIH(DC)
0.780V
0.765V
0.750V
0.735V
0.720V
0.780V
0.765V
0.750V
0.735V
0.720V
0.650V
0.575V
VIL(DC)
VIL(AC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.650V
VIL(DC)
0.575V
VIL(AC)
0.0V
VSS
VSS - 0.4V narrow
pulse width
–0.40V
Notes:
1. Numbers in diagrams reflect nominal values.
AC Overshoot/Undershoot Specification
Table 23:
Control and Address Pins
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Maximum peak amplitude allowed for overshoot area
(see Figure 18 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 19 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD (see Figure 18 on page 43)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
Maximum undershoot area below VSS (see Figure 19 on page 43)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Table 24:
Clock, Data, Strobe, and Mask Pins
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Maximum peak amplitude allowed for overshoot area
(see Figure 18 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 19 on page 43)
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD/VDDQ
(see Figure 18 on page 43)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
Maximum undershoot area below VSS/VSSQ
(see Figure 19 on page 43)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
Figure 18: Overshoot
Maximum amplitude
Overshoot area
Volts (V)
VDD/VDDQ
Time (ns)
Figure 19: Undershoot
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Table 25:
Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
All voltages are referenced to VSS
Parameter/Condition
Differential input voltage
Symbol
Min
Max
Units
VIN
–400
VDD + 400
mV
Differential input midpoint voltage
VMP(DC)
650
850
mV
Differential input voltage logic high
VIHDIFF
200
VDD + 400
mV
Differential input voltage logic low
VILDIFF
VSSQ - 400
–200
mV
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
VREF(DC) - 175
VREF(DC) + 175
mV
VREF(DC) - 150
VREF(DC) + 150
mV
Differential input crossing voltage relative
to VDD/2 for CK, CK#
Differential input crossing voltage relative
to VDD/2 for DQS, DQS#
Notes:
1. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#) level.
VMP(DC) is expected to be about 0.5 × VDDQ.
2. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
3. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe.
4. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
5. Differential input slew rate = 2 V/ns.
6. The VIX extended range (±175mV) is allowed only for the clock. Additionally, the VIX
extended range is only allowed when the following conditions are met: The single-ended
input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2
±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns.
Figure 20: Single-Ended Requirements for Differential Signals
VDD or VDDQ
VSEH (MIN)
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL (MAX)
VSEL
VSS or VSSQ
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Figure 21: Definition of Differential AC-Swing and tDVAC
tDVAC
VIHDIFF(AC) MIN
VIHDIFF (MIN)
VIHDIFF(DC) MIN
CK - CK#
DQS - DQS#
0.0
VILDIFF(DC) MAX
VILDIFF (MAX)
VILDIFF(AC) MAX
tDVAC
half cycle
Table 26:
Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS#
Below VIL(AC)
Slew Rate (V/ns)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. F 11/08 EN
tDVAC
(ps) at |VIHDIFF(AC)/VILDIFF(AC)|
350mV
300mV
>4.0
75
175
4.0
57
170
3.0
50
167
2.0
38
163
1.9
34
162
1.6
29
161
1.4
22
159
1.2
13
155
1.0
0
150
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